Team Members

Jie Liang, Associate Professor

Email: liangjieclair@shu.edu.cn

Personal Profile:

Engaged in the research of advanced micro-nano electronic materials, devices and on-chip advanced interconnection applications beyond Moore, the research of radio frequency devices based on SOI, the design of wearable flexible devices and biological signal amplification circuits, and the research of health monitoring and detection sensors and systems. More than 40 papers have been published in related fields, such as IEDM, Symp. VLSI, TED, EDL, JEDS, etc. More than 10 patents have been applied for, and 2 patents have been authorized by the EU. Presided over the National Natural Science Foundation of China 1. During the doctoral period, she participated in two large-scale EU Horizon project H2020 for three consecutive years. In March 2022, it was selected into Shanghai 's overseas high-level talent introduction plan.

Postgraduates with related professional backgrounds such as microelectronics, electronic information, applied physics, material engineering, and mechanical engineering are recruited.

Research Direction:

1.Physical modeling and circuit design of advanced micro-nano electronic devices ( reconfigurable devices, SOI RF devices ) ;

2.Advanced on-chip interconnection modeling and application ( carbon-based interconnection, TSV, back power supply ) ;

3.Health monitoring and detection sensors and systems ( flexible sensing, sweat sensing, microneedle diagnosis and treatment integration ).

Educational Background:

In 2019, she graduated from the University of Montpellier, France, majoring in microelectronics.

In 2016, she graduated from the University of Paris in quantum device science.

In 2014, she graduated from the University of Paris, majoring in physics.

Work Experience:

March 2022 - So far Associate Professor and Master Supervisor of Shanghai University.

March 2021 - March 2022 Lecturer, Distinguished Associate Professor and Master Supervisor, Shanghai University.

August 2019 - December 2020 Postdoctoral Fellow, National University of Singapore.

Scientific research achievements and awards:

More than 40 SCI and EI papers have been published in related fields, more than 10 patents have been applied, and 2 patents have been authorized by the EU. Presided over the National Natural Science Foundation of China 1.

It won the eighth National College Students ' Integrated Circuit Innovation and Entrepreneurship Competition, the fourteenth " Self-Strengthening Cup " College Students ' Extracurricular Academic and Technological Works Competition, the excellent instructor of Shanghai University 's summer social practice in 2023, and the advanced individual of Shanghai University 's international work in 2022.

Representative Results:

1.Baohui Xu; Rongmei Chen; Jiuren Zhou; Jie Liang*; A Modeling Study on Electrical and Thermal Behavior of CNT TSV for Multilayer Structure, [J]. IEEE Transactions on Electron Devices, 2023, 70(9): 4779-4785

2.Baohui Xu; Rongmei Chen; Jiuren Zhou; Jie Liang*; A Modeling Study of Stacked Cu-CNT TSV on Electrical, Thermal, and Reliability Analysis, [J]. IEEE Transactions on Electron Devices, 2023, 71(1): 184-191

3.Zhenbang Chu; Baohui Xu; Jie Liang*; Direct Application of Carbon Nanotubes (CNTs) Grown by Chemical Vapor Deposition (CVD) for Integrated Circuits (ICs) Interconnection: Challenges and Developments, [J]. Nanomaterials, 2023, 13(20)

4.Liang J, Sun C, Xu H, et al. Strained Silicon-on-Insulator Platform for Co-Integration of Logic and RF—Part II: Comb-Like Device Architecture [J]. IEEE Transactions on Electron Devices, 2022, 69(4): 1769-75.

5.Xu B, Chen R, Zhou J, and Liang J*. Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects [J]. Micromachines, 2022, 13(7): 1148.

6.S. Chen#, J. Liang#, et al. and G. Xiao*, " Enabling UTBB Strained SOI Platform for Co-integration of Logic and RF: Implant-Induced Strain Relaxation and Comb-like Device Architecture,” in Symp. on VLSI Tech. 2020 (VLSI 2020), USA, Jun. 14-19, 2020.

7.J. Liang and A. Todri-Sanial, "Importance of Interconnects: A Technology System-Level Design Perspective,” will be presented in IEEE International Electron Devices Meeting (IEDM), San Francisco, December 2019. (Invited paper)

8.J. Liang, et al. and A. Todri-Sanial, “Investigation of Pt-Salt Doped Stand-Alone Multi-Wall Carbon Nanotubes for On-Chip Interconnect Applications,” IEEE Transactions on Electron Devices, 2019. doi: 10.1109/TED.2019.2901658.

9.J. Liang, et al., “Atomistic to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects,” IEEE Transactions on Nanotechnology, 2018, doi: 10.1109/TNANO.2018.2802320.

10.J. Liang, et al., "A Physics-Based Investigation of Pt-Salt Doped Carbon Nanotubes for Local Interconnects,” in IEEE International Electron Devices Meeting (IEDM), San Francisco, December 2017, pp. 35.5.1-35.5.4. doi: 10.1109/IEDM.2017.8268502.